Ordering Within a Virtual Channel (VC)

• Normally, packets within the same VC are sent in the exact order they were received.
• This ensures that memory operations, I/O operations, etc. that are meant to happen sequentially do so.
• Example: if you send a memory write followed by a memory read, you expect the read to reflect the written value — so PCIe makes sure the write is completed first (within that VC).

2. Relaxed Ordering

• PCIe supports a “relaxed ordering” attribute on packets (inherited from PCI-X).
• If relaxed ordering is set, the packet can bypass earlier packets in the queue to improve throughput.
• This is useful for bulk DMA transfers where exact ordering doesn’t matter — e.g., network card writing buffers into RAM where the software doesn’t depend on order.

3. Ordering Across Virtual Channels

• Ordering rules only apply within a VC.
• If packets are in different VCs (thus potentially different TCs), they are considered independent.
• The hardware is free to interleave them however it likes.
• Software must assume no ordering relationship between packets using different TCs.

4. Why This Matters (Deadlock/Livelock Prevention)

• Strict ordering prevents deadlock where one transaction is waiting on another that never completes.
• Relaxed ordering gives performance flexibility while still ensuring that critical dependencies are respected.

5. Transaction Layer Responsibility

• Ordering is maintained within the Transaction Layer of PCIe.
• Once packets are mapped to their VC, the TL ensures they exit in the right sequence (unless relaxed ordering is allowed).

So, big picture:

• Within the same VC → ordered (unless relaxed ordering is explicitly used).
• Across VCs / TCs → no guaranteed ordering (software must not rely on it).
• This model strikes a balance between correctness and high throughput.